library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ImageControllerTestbench is
end ImageControllerTestbench;

architecture test of ImageControllerTestbench is

  component ImageController is
    Port(IMG_Data : in std_logic_vector(9 downto 0);
			IMG_PIXEL_Clk : in std_logic;
			IMG_ROW_EN : in std_logic;
			IMG_RST : out std_logic;
			
			OEM_Data : out std_logic_vector(9 downto 0);
			OEM_PIXEL_Clk : out std_logic;
			OEM_ROW_EN : out std_logic;
			OEM_VSYNC : out std_logic);
  end component;
  
  component ImageDataGen2 is
    Port(PixelClk : out std_logic;
         Data : out std_logic_vector(15 downto 0);
         RowEN : out std_logic);  
  end component;
  
  signal pclk,rowen,fpgaClk,rst : std_logic:='0';
  signal data,OEM_Data : std_logic_vector(15 downto 0);
  signal OEM_Pixel_Clk,OEM_Row_Clk,OEM_Row_EN,OEM_VSYNC : std_logic;
  signal SW,LED : std_logic_vector(3 downto 0):="0000";
  signal IMG_I2C_Clk,IMG_I2C_Data,OEM_I2C_CLk,OEM_I2C_Data : std_logic;

begin
  
  fpgaClk<=not fpgaClk after 5 ns;
  
  Ctrlr: ImageController port map(data(9 downto 0),pclk,rowen,rst,OEM_Data(9 downto 0),OEM_Pixel_Clk,OEM_Row_EN,OEM_VSYNC);
  Imager: ImageDataGen2 port map(pclk,data,rowen);
  
end test;